Detailed Calculation of MIPI SerDes Bandwidth

2025-11-21

***Take the 4K Display and 40-megapixel Camera as examples.

In all high-speed interface designs, bandwidth calculation is not a formality but directly determines:

• Whether the interface is affordable
• How many lanes to use
• Whether to reserve upgrade headroom
• Whether it will be rendered obsolete by future “resolution upgrades”

Below we calculate using two most typical engineering scenarios:
👉 4K Display (DSI / SerDes)
👉 40MP Camera (CSI / SerDes)

I. Standardize a “project-ready” calculation method.

Whether it’s DSI, CSI, GMSL, FPD-Link, or MIPI M-PHY,
The underlying logic remains consistent:

Effective data volume × Protocol overhead ÷ Number of lanes ÷ Encoding efficiency

Universal Formula (Engineering Edition)

Single Lane Rate (bps) =（Resolution × Frame Rate × Bit Depth per Pixel × Protocol Coefficient）/ (Number of Lanes × Encoding Efficiency)

Among these:
Protocol Coefficient: Empty lines, Blank, Header, CRC, etc.
Typically set to 1.2–1.3 in engineering practice
Encoding Efficiency:
*8b/10b → 0.812
*8b/130b → 0.985
*RAW → 1.0

📌 Note:
The minimum standard value ≠ the engineering safety value.
Design must always include a margin of safety.

II. 4K Display Bandwidth Calculation

1️⃣ Basic Parameter Assumptions (Very Typical)

Let’s select a common specification for an in-car infotainment system:

• Project Resolution: 3840 × 2160
• Frame Rate: 60 fps
• Pixel Format: RGB888
• Bit Depth per Pixel: 24 bits

2️⃣ Calculation of Raw Video Data Volume

• Pixels per frame = 3840 × 2160 = 8,294,400 pixels
• Pixels per second = 8,294,400 × 60 ≈ 497,664,000 pixels/s
• Raw data volume = 497,664,000 × 24 ≈ 11.94 Gbps

3️⃣ Plus display interface overhead / synchronization overhead

Display interface (DSI/SerDes) must include:
>> HSYNC
>> VSYNC
>> Front/Back Porch

Commonly used in engineering:

• Agreement coefficient ≈ 1.25
• Actual required bandwidth ≈ 11.94 × 1.25 ≈ 14.9 Gbps

4️⃣ Assuming the use of 4-lane SerDes / DSI

• Load per lane ≈ 14.9 / 4 ≈ 3.7 Gbps

If the interface uses 8b/10b encoding:

• Actual lane rate ≈ 3.7 / 0.8 ≈ 4.6 Gbps

📌 Engineering Conclusions:

4K@60Hz RGB888, 4-lane system, Each lane must support at least 5 Gbps for safety.

This is why:

• D-PHY is struggling
• M-PHY / GMSL2 / FPD-Link III are just starting to feel comfortable

III. 40-Megapixel Camera Bandwidth Calculation

Now let’s calculate a real bandwidth hog.

1️⃣ Camera Parameter Settings

Project

• Resolution: 8000 × 5000 pixels
• Number of Pixels: 40 MP
• Frame Rate: 30 fps
• Data Format: RAW10

2️⃣ Calculation of Raw Data Volume

• Pixels per frame = 8000 × 5000 = 40,000,000 pixels
• Pixels per second = 40,000,000 × 30 = 1.2 × 10⁹ pixels/s
• Raw data volume = 1.2 × 10⁹ × 10 = 12 Gbps

👉 Note: RAW10 is 10 bits per pixel.

3️⃣ Plus CSI/SerDes protocol overhead

CSI has:

• Packet Header
• ECC
• CRC
• Line blank

Engineering Experience:

• Agreement coefficient ≈ 1.2
• Actual data volume ≈ 12 × 1.2 = 14.4 Gbps

4️⃣ Assuming the use of a 2-lane high-speed SerDes

• Load per lane ≈ 14.4 / 2 = 7.2 Gbps

If 8b/10b encoding is used:

• Actual lane rate ≈ 7.2 / 0.8 = 9 Gbps

📌 The engineering conclusion is brutally harsh:

• 40MP@30fps, 2-lane system, A single lane requires nearly 10 Gbps

Here’s why:

• Traditional CSI-2 simply can’t handle it
• Must implement: GMSL2 / GMSL3
• FPD-Link IV
• or M-PHY High Gear

IV Engineer’s Safety Factor Principle

• Design Bandwidth ≥ Theoretical Demand × 1.3

4K Display:
Calculated at 4.6 Gbps, select 6 Gbps PHY
40MP Camera:
Calculated at 9 Gbps, directly select 10~12 Gbps range

V. Translate the calculation results into the language of solution selection.

4K Display

Solution Evaluation

• D-PHY 4-lane: Marginal performance
• D-PHY 8-lane: High cost
• M-PHY: Cost-effective
• GMSL2 / FPD-Link III: Engineering-friendly

40MP Camera

Conclusion of the Proposal

• CSI-2 D-PHY: Not feasible
• M-PHY High Gear: Challenging
• GMSL2: Marginal
• GMSL3 / FPD-Link IV: The correct solution

VI. Conclusion

SerDes bandwidth calculation isn’t just math—it’s the lifeline of system design.
Get it right, and your solution stands firm;
Get it wrong, and resolution and frame rate will come back to bite you later.