2025-12-18
Background Information:
The product architecture is as follows: the signal source is a universal display chip outputting HDMI TMDS signals. These signals are converted to EDP format via an FPGA and displayed on an EDP monitor. The issue encountered is abnormal EDP display functionality under specific conditions, resulting in screen flickering. After debugging, adjusting the constant current source gain at the HDMI source end (adjustable from 1mA to 6mA) resolves this functional issue at specific values (3mA and 4mA). At specific values (3mA and 4mA), this resolves the functionality issue. Signal testing is required to determine the optimal current gain setting, followed by refinement of the technical report to gain final customer approval.
Test Analysis: EDP Port
Upon receiving this signal analysis task, and with an understanding of the product architecture, considering that the issue involves screen flickering on the EDP display, the first step is to inspect whether the signal at the EDP output varies under different current gain settings. Since EDP consistency testing requires transmitting specific test patterns, and the current environment could not control the FPGA chip to send these patterns. The solution employed was to use the Quick Eye function of an oscilloscope on the EDP display side during EDP operation to generate an eye diagram of the actual transmitted signal. The waveform diagram is shown below:
The following phenomena were observed:
Phenomenon 1: The EDP is indeed operating at the expected 2.7Gbps rate.
Phenomenon 2: The measured eye height is approximately 250mV, meeting the level requirements defined for EDP panels.
Phenomenon 3: At gain settings of EDP: 1mA/2mA/3mA/4mA/5mA/6mA, the eye height and eye width exhibit minimal variation.
Test Analysis: HDMI Port
After the above tests, from the perspective of signal testing at the backend EDP end, no useful information explaining the screen flickering anomaly was found. The task remained unresolved, so attention naturally shifted to the frontend HDMI end. The modified gain value also corresponds to the frontend HDMI Source value. Analyzing this, theoretically, there should be a difference.
Referring to this architecture diagram, the HDMI TMDS signal undergoes a 3.3V pull-up operation. The rear-end EDP display functions, and the FPGA chip operates. For HDMI compliance testing, only normal TMDS signal output is required—specific test patterns need not be run. Running HDMI compliance tests here is feasible. However, since testing occurs along the signal path, it cannot replicate standard HDMI interface testing using fixtures with SMA probes. Our approach involves using an E2677A solder probe to capture waveforms before and after the capacitor. Since the waveform trends are similar before and after the capacitor, the following analysis primarily focuses on the waveform before the capacitor.
Based on preliminary signal quality observations, the HDMI TMDS clock operates at 148.5MHz. To meet the clock requirements for 1080p resolution and hardware design specifications, a consistency analysis is conducted at 1080p resolution.
Since the test points are located at the front end of the capacitor rather than at the test points defined for consistency testing, we only use consistency analysis methods to compare differences. From the diagrams above, it appears that generally, the greater the current gain, the wider the eye opens. Observing solely from the eye diagrams, the results at 5mA are the most visually appealing. The other eye diagrams either exhibit excessive noise or suggest slightly insufficient drive capability.
However, HDMI testing requires compliance with numerous parameters beyond just the eye diagram. At current gains of 1mA, 2mA, and 3mA, all tests pass except for the Data Mask Test Fail. When the current reaches 4mA and above, the Rise/Fall Time begins to exceed specification requirements. Excessively fast Rise/Fall Times indicate higher high-frequency components on the signal edge. This increases susceptibility to energy leakage, potentially causing near-end and far-end crosstalk, electromagnetic interference, and other adverse effects.
Based on comprehensive functional observations, the 3mA/4mA configuration exhibits no functional anomalies even under the stringent conditions established by end customers. Combining this with the evidence chain from the aforementioned signal tests, a comprehensive assessment indicates that the 3mA gain effectively balances the impact on the eye diagram and edge response. Consequently, the product’s gain has been finalized at 3mA.